? semiconductor components industries, llc, 2002 march, 2002 rev. 1 1 publication order number: nstb60adw1t1/d nstb60adw1t1 pnp general purpose and npn bias resistor transistor combination ? simplifies circuit design ? reduces board space ? reduces component count ? available in 8 mm, 7 inch/3000 unit tape and reel ? esd rating human body model: class 1b esd rating machine model: class b maximum ratings (t a = 25 c unless otherwise noted, common for q 1 and q 2 ) rating symbol q 1 q 2 unit collector-emitter voltage v ceo 50 50 vdc collector-base voltage v cbo 50 50 vdc emitterbase voltage v ebo 6.0 5.0 vdc collector current continuous i c 150 150 madc thermal characteristics characteristic (one junction heated) symbol max unit total device dissipation t a = 25 c derate above 25 c p d 187 (note 1) 256 (note 2) 1.5 (note 1) 2.0 (note 2) mw mw/ c thermal resistance junction-to-ambient r q ja 670 (note 1) 490 (note 2) c/w characteristic (both junctions heated) symbol max unit total device dissipation t a = 25 c derate above 25 c p d 250 (note 1) 385 (note 2) 2.0 (note 1) 3.0 (note 2) mw mw/ c thermal resistance junction-to-ambient r q ja 493 (note 1) 325 (note 2) c/w thermal resistance junction-to-lead r q jl 188 (note 1) 208 (note 2) c/w junction and storage temperature t j , t stg 55 to +150 c 1. fr4 @ minimum pad 2. fr4 @ 1.0 x 1.0 inch pad sot363 case 419b style 1 marking diagram q 1 r 2 r 1 q 2 (1) (2) (3) (4) (5) (6) 1 2 3 6 5 4 device package shipping ordering information nstb60adw1t1 sot363 3000/tape & reel 70 d 70 = specific device code d = date code http://onsemi.com
nstb60adw1t1 http://onsemi.com 2 electrical characteristics (t a = 25 c unless otherwise noted) characteristic symbol min typ max unit q 1 collector-base breakdown voltage (i c = 50 m adc, i e = 0) v (br)cbo 50 vdc collector-emitter breakdown voltage (i c = 1.0 madc, i b = 0) v (br)ceo 50 vdc emitterbase breakdown voltage (i e = 50 adc, i e = 0) v (br)ebo 6.0 vdc collectorbase cutoff current (v cb = 50 vdc, i e = 0) i cbo 0.1 a emitterbase cutoff current (v eb = 6.0 vdc, i b = 0) i ebo 0.1 a collector-emitter saturation voltage (i c = 50 madc, i b = 5.0 madc) (note 3) v ce(sat) 0.5 vdc dc current gain (v ce = 10 v, i c = 5.0 ma) (note 3) h fe 120 560 transition frequency (v ce = 12 vdc, i c = 2.0 madc, f = 100 mhz) f t 140 mhz output capacitance (v cb = 12 vdc, i e = 0 adc, f = 1.0 mhz) c ob 3.5 pf q 2 collector-base breakdown voltage (i c = 50 m a, i e = 0) v (br)cbo 50 vdc collector-emitter breakdown voltage (i c = 1.0 ma, i b = 0) (note 3) v (br)ceo 50 vdc collectorbase cutoff current (v cb = 50 v, i e = 0) i cbo 100 nadc collectoremitter cutoff current (v ce = 50 v, i b = 0) i ceo 500 nadc emitterbase cutoff current (v eb = 6.0 v, i c = 0) i ebo 0.15 madc collector-emitter saturation voltage (i c = 10 ma, i b = 5.0 ma) (note 3) v ce(sat) 0.25 vdc dc current gain (v ce = 10 v, i c = 5.0 ma) (note 3) h fe 40 output voltage (on) (v cc = 5.0 v, v b = 4.0 v, r l = 1.0 k ) (note 3) v ol 0.2 vdc output voltage (off) (v cc = 5.0 v, v b = 0.25 v, r l = 1.0 k ) (note 3) v oh 4.9 vdc input resistor (note 3) r1 32.9 47 61.1 k w resistor ratio (note 3) r1/r2 3.76 4.7 5.64 3. pulse test: pulse width < 300 m s, duty cycle < 2.0%
nstb60adw1t1 http://onsemi.com 3 typical electrical characteristics pnp transistor 2.0 1.5 1.0 0.2 0.3 0.5 0.7 -200 -0.2 -0.5 -1.0 -2.0 -5.0 -10 -20 -50 -100 i c , collector current (madc) figure 1. normalized dc current gain h fe , normalized dc current gain v ce = -10 v t a = 25 c -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 -0.1 i c , collector current (madc) figure 2. asaturationo and aono voltages v, voltage (volts) t a = 25 c v be(sat) @ i c /i b = 10 v be(on) @ v ce = -10 v v ce(sat) @ i c /i b = 10 400 20 30 40 60 80 100 200 300 i c , collector current (madc) figure 3. currentgain bandwidth product f t , current-gain bandwidth product (mhz) c, capacitance (pf) 10 1.0 2.0 3.0 5.0 7.0 -0.4 v r , reverse voltage (volts) figure 4. capacitances t a = 25 c c ib c ob r b , base spreading resistance (ohms) 150 140 130 120 110 100 i c , collector current (madc) figure 5. output admittance -0.2 -0.5 -1.0 -2.0 -5.0 -10 -20 -50 -100 v ce = -10 v t a = 25 c -0.5 -1.0 -2.0 -3.0 -5.0 -10 -20 -30 -50 -0.6 -1.0 -2.0 -4.0 -6.0 -10 -20 -30 -40 1.0 i c , collector current (madc) figure 6. base spreading resistance v ce = -10 v f = 1.0 khz t a = 25 c -0.1 -0.2 -0.3 -0.5 -1.0 -2.0 -3.0 -5.0 -10 v ce = -10 v f = 1.0 khz t a = 25 c -0.1 -0.2 -0.5 -1.0 -2.0 -5.0 -10 0.01 0.03 0.05 0.1 0.3 0.5 h , output admittance (ohms) ob 150
nstb60adw1t1 http://onsemi.com 4 typical electrical characteristics npn brt t a = 85 c 25 c 40 c t a = 40 c 100 10 0.01 0.1 1 01020 i c , collector current (ma) figure 7. maximum collector voltage versus collector current i c /i b = 10 1000 100 1 0 1 i c , collector current (ma) figure 8. dc current gain 3 0 0.5 1 1.5 2.5 v r , reverse voltage (v) figure 9. output capacitance 100 1 10 0 i c , collector current (ma) figure 10. input voltage versus output voltage figure 11. input voltage versus output current 10 100 010 60 10203040 5 060 100 i c , collector current (ma) 0102030405060 1 10 2 30 40 50 60 70 80 v ce(sat) , maximum collector voltage (v) 25 c 85 c h fe , dc current gain v ce = 10 v 20 30 40 50 c ob , capacitance (pf) f = 1 mhz t a = 25 c v in , input voltage (v) t a = 40 c 25 c 85 c v in , input voltage (v) t a = 40 c 25 c 85 c v o = 0.2 v
nstb60adw1t1 http://onsemi.com 5 0.5 mm (min) 0.4 mm (min) 0.65 mm 0.65 mm 1.9 mm the values for the equation are found in the maximum ratings table on the data sheet. substituting these values into the equation for an ambient temperature t a of 25 c, one can calculate the power dissipation of the device which in this case is 256 milliwatts. information for using the sot363 surface mount package minimum recommended footprint for surface mounted applications surface mount board layout is a critical portion of the total design. the footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. with the correct pad geometry, the packages will self align when subjected to a solder reflow process. sot363 power dissipation p d = t j(max) t a r q ja p d = 150 c 25 c 490 c/w = 256 milliwatts the power dissipation of the sot363 is a function of the pad size. this can vary from the minimum pad size for soldering to a pad size given for maximum power dissipa- tion. power dissipation for a surface mount device is deter- mined by t j(max) , the maximum rated junction temperature of the die, r q ja , the thermal resistance from the device junction to ambient, and the operating temperature, t a . using the values provided on the data sheet for the sot363 package, p d can be calculated as follows: the 490 c/w for the sot363 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 256 milli- watts. there are other alternatives to achieving higher power dissipation from the sot363 package. another alternative would be to use a ceramic substrate or an aluminum core board such as thermal clad ? . using a board material such as thermal clad, an aluminum core board, the power dissipation can be doubled using the same footprint. soldering precautions the melting temperature of solder is higher than the rated temperature of the device. when the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. there- fore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. ? always preheat the device. ? the delta temperature between the preheat and soldering should be 100 c or less.* ? when preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. when using infrared heating with the reflow soldering method, the difference shall be a maximum of 10 c. ? the soldering temperature and time shall not exceed 260 c for more than 10 seconds. ? when shifting from preheating to soldering, the maximum temperature gradient shall be 5 c or less. ? after soldering has been completed, the device should be allowed to cool naturally for at least three minutes. gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. ? mechanical stress or shock should not be applied during cooling. * soldering a device without preheating can cause exces- sive thermal shock and stress which can result in damage to the device. sot363
nstb60adw1t1 http://onsemi.com 6 step 1 preheat zone 1 ramp" step 2 vent soak" step 3 heating zones 2 & 5 ramp" step 4 heating zones 3 & 6 soak" step 5 heating zones 4 & 7 spike" step 6 vent step 7 cooling 200 c 150 c 100 c 50 c time (3 to 7 minutes total) t max solder is liquid for 40 to 80 seconds (depending on mass of assembly) 205 to 219 c peak at solder joint desired curve for low mass assemblies 100 c 150 c 160 c 140 c figure 12. typical solder heating profile desired curve for high mass assemblies 170 c for any given circuit board, there will be a group of control settings that will give the desired heat pattern. the operator must set temperatures for several heating zones, and a figure for belt speed. taken together, these control settings make up a heating aprofileo for that particular circuit board. on machines controlled by a computer, the computer remembers these profiles from one operating session to the next. figure 12 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. this profile will vary among soldering systems but it is a good starting point. factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. this profile shows temperature versus time. solder stencil guidelines prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. a solder stencil is required to screen the optimum amount of solder paste onto the footprint. the stencil is made of brass or stainless steel with a typical thickness of 0.008 inches. the stencil opening size for the surface mounted package should be the same as the pad size on the printed circuit board, i.e., a 1:1 registration. typical solder heating profile the line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. the two profiles are based on a high density and a low density board. the vitronics smd310 convection/infrared reflow soldering system was used to generate this profile. the type of solder used was 62/36/2 tin lead silver with a melting point between 177189 c. when this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. the components on the board are then heated by conduction. the circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.
nstb60adw1t1 http://onsemi.com 7 package dimensions sot363 case 419b02 issue j notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. dim a min max min max millimeters 1.80 2.20 0.071 0.087 inches b 1.15 1.35 0.045 0.053 c 0.80 1.10 0.031 0.043 d 0.10 0.30 0.004 0.012 g 0.65 bsc 0.026 bsc h --- 0.10 --- 0.004 j 0.10 0.25 0.004 0.010 k 0.10 0.30 0.004 0.012 n 0.20 ref 0.008 ref s 2.00 2.20 0.079 0.087 b 0.2 (0.008) mm 123 a g s h c n j k 654 b d 6 pl style 1: pin 1. emitter 2 2. base 2 3. collector 1 4. emitter 1 5. base 1 6. collector 2
nstb60adw1t1 http://onsemi.com 8 on semiconductor is a trademark and is a registered trademark of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circui t, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may b e provided in scillc data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its paten t rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. nstb60adw1t1/d thermal clad is a registered trademark of the bergquist company. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada
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